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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
9ms
9ms
80ms
150ms
t DET(1)
150ms
t DET(2)
19ms
t CLASS(1)
19ms
t CLASS(2)
t
0V
-4V
-9.1V
-18V
-54V
V OUT_ - V AGND
Figure 2. Detection, 2-Event Classification, and Port Power-Up Sequence
V RSENSE_ exceeds V CUT and decreases at a slower
pace when V RSENSE_ drops below V CUT . A slower
decrement for the t FAULT counter allows for detecting
repeated short-duration overcurrent conditions. When
the counter reaches the t FAULT limit, the device powers
the port down and asserts the corresponding TCUT_
bit (R06h[3:0] and R07h[3:0], Table 10). For a continu-
ous overstress, a fault latches exactly after a period of
t FAULT . V CUT is programmable through the ICUT_
registers (Table 40). If a port is powered down due to
a current-limit condition, during normal operation, the
device asserts the corresponding ICV_ bit (R08h[7:4]
and R09h[7:4], Table 11)
After power-off due to an overcurrent fault, the t FAULT
timer is not immediately reset but starts decrementing
at the same slower pace. The device allows a port to be
powered on only when the t FAULT counter is at zero. This
feature sets an automatic duty-cycle protection to the
external MOSFET to avoid overheating.
High-Power Mode
The device features individual, port programmable high-
power settings. To enable the high-power configuration
for a port, set the corresponding HP_EN_ bit (R44h[3:0],
Table 38) to 1. By default, if AUTO = 1, the HP_EN_ bits
will be set to 1 automatically after a reset event. When
enabled, each port’s high-power settings can be indi-
vidually configured using the corresponding Port GPMD,
Port Overcurrent (ICUT), Port Current-Limit (ILIM_), and
Port High-Power Status registers (see the Register Map
and Description section, Tables 39–42).
19
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